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fn6456 rev 1.00 page 1 of 30 august 25, 2011 fn6456 rev 1.00 august 25, 2011 ISL6112 dual slot pci-express hot plug controller datasheet the ISL6112 targets the pci-express add-in card hot plug application. together with two each of n-channel and p-channel mosfets, four current sense resistors, and several external passive components, the ISL6112 provides a compliant hot plug power control solution to any combination of two pci-express x1, x4, x8 or x16 slots. the ISL6112 features the ability to program a maximum current regulated level for each of the main outputs for a common programmable duration. wi th this ability, both fault isolation protection and impervio usness to electrical transients (oc and soft-start protection) are provided to each system supply. for each 12vmain supply, the current regulated (cr) level is set by a resistor valu e dependent on the size of the pci-express connector (x1, x4/x8 or x16) to be powered. this resistor is a sub ohm standard value current sense resistor; one each for each of the 3vma in and 12vmain supplies. the voltage across this resistor is compared to a 50mv reference, providing a nominal cr protection level that would be set above the maximum specified slot limits. the 3.3v supply can use a 15m sense resistor, compared to a 50mv reference, to provide a nominal regulated current limit of 3.3a to all connector sizes. a shutdown without a cr duration delay is invoked if rsense voltage is >100mv. vaux is internally monitored and controlled to prov ide nominal limiting to 1a of load current. the ISL6112 is system management interface (smi) capable, with an integrated smbus link for communication, control, monitoring, and reporting of ic and slot conditions. information such as uv, oc, status, and power level are available. additionally, the ic has a minimum of i/o for implementations where hot-plug hardware interface (hpi) is implemented. features ? supports two independent pci-express slots ? highest available accuracy external rsense current monitoring on main supplies ? programmable current regulation protection function for x1, x4, x8, x16 connectors ? 12v, 3.3v, and 3.3vaux supplies supported per pci express specification v1.0a ? voltage tolerant i/o smbus interface for slot power control and status, compatible with smbus 2.0 systems ? programmable current regulation duration ? programmable in-rush current limiting ? dual-level fault detection for quick fault response without nuisance tripping ? slot-to-slot electrical and thermal isolation ? two general-purpose input pins suitable for interface to logic and switches ? pb-free (rohs compliant) applications ? pci express v1.0a hot-plug power control ? pci-express servers ? power supply distribution and control figure 1. fast trip threshold voltage vs temperature figure 2. aux current limit vs temperature 96 97 98 99 100 101 102 103 104 -60 -40 -20 0 20 40 60 80 100 120 woc threshold voltage (v) temperature (c) 800 850 900 950 1000 1050 1100 1150 1200 -60 -40 -20 0 20 40 60 80 100 120 aux current limit (ma) temperature (c) o b s o l e t e p r o d u c t n o r e c o m m e n d e d r e p l a c e m e n t c o n t a c t o u r t e c h n i c a l s u p p o r t c e n t e r a t 1 - 8 8 8 - i n t e r s i l o r w w w . i n t e r s i l . c o m / t s c
ISL6112 fn6456 rev 1.00 page 2 of 30 august 25, 2011 typical application diagram system power supply pci-express connector +12v +3.3v vstby vstbyb vstbya vauxa 12vina 12vsensea 3vina 3vsensea 12vinb 12vsenseb 3vinb 3vsenseb 12vgatea 12vouta 3vgatea 3vouta 3vgateb 3voutb vauxb gnd gnd a1 a2 a0 onb ona gpi_b0 gpi_a0 force_on b force_on a auxenb auxena int scl sda 12vgateb 12voutb cfiltera cfilterb ISL6112 #cgs 22nf * r12vgatea 15 ? # c gate 22nf # cgd 6800pf 15 ? rsense^ pci express bus 3.3aux 375ma 3.3v 3.0a 12v 2.1a (x4/x8) rsense^ #cgs 22nf * r12vgateb 15 ? # cgd 6800pf rsense^ 0.015 ? #cgate 22nf *r3vgateb rsense^ 0.015 ? pci-express connector pci express data bus 3.3aux 375ma 3.3v 3.0a 12v 2.1a (x4/x8) * values for r 12vgate and r 3vgate may vary depending upon the c gs of the external mosfets. # these components are not required for ISL6112 operation but can be implemented for gate output slew rate control (application specific). ? bold lines indicate high current paths. 4 9 2 11 26 5 8 3 10 12 13 14 16 32 29 34 27 25 24 23 21 22 17 gnd 33 46 15 15 ? *r3vgatea 0.1f 0.1f 0.1f 0.1f 0.1f 0.1f fault b fault a pwrgd b pwrgd a 1 onb ona auxenb auxena int scl sda hot-plug controller smbus i/o management controller 48 47 37 43 42 38 28 35 45 44 v stby c1 c2 vstby 10k x 3 10k x 4 sda scl int smbus base address 39 40 41 gpi_b0 100k 100k 100k 100k gpi_a0 v stby force_on b force_on a faultb faulta pwrgdb pwrgda 36 31 6 v stby 10k x 4 ^ r sense value is application specific.
ISL6112 fn6456 rev 1.00 page 3 of 30 august 25, 2011 functional block diagram (one channel) logic circuits vaux pwrgd thermal shutdown on/off vaux charge pump and mosfet vaux overcurrent 3vin 10.5v 2.8v digital core/serial interface 12vin 12v bias power-on reset 250s 3v uvlo 12v uvlo on /off on /off on /off on / 50mv 50mv 100mv* 100mv* vstby i ref vstby 40k ? x 3 12vgate vaux 3vgate pwrgd fault 3vout 12vout 3vpwrgd 12vpwrgd int gnd a0 a1 a2 sda scl gpi force _on cfilter 3vin 3vsense 12vin 12vsense on auxen vstby vstby uvlo off 1.25v both a and b slots share th e scl, sda, a0, a1, a2, int pins.
ISL6112 fn6456 rev 1.00 page 4 of 30 august 25, 2011 pin configuration ISL6112 (48 ld 7x7 qfn) top view 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 gnd (exposed bottom pad) gnd 3vouta vauxa 3vgatea 3vsensea nc nc 3voutb vauxb 3vgateb 3vsenseb auxena gnd scl sda ona onb auxenb a0 a1 a2 gpi_b0 fault b cfilterb 12vgateb gnd 12vinb pwrgd b nc 12vsenseb force_on b 12voutb vstbyb 3vinb fault a cfiltera 12vgatea gpi_a0 12vina pwrgd a nc 12vsensea force_on a 12vouta vstbya 3vina nc int pin descriptions pin number pin name pin function 5, 32 12vina, 12vinb provides 12vmain power supply and the high side of the sense resistor inputs. this must be a kelvin connection between ic and sense resistor. an undervolta ge lockout circuit (uvlo) prevents the switches from turning on while this input is less than its lockout threshold. 12, 25 3vina, 3vinb provides 3.3vmain power supply and the high side of the sense resistor inputs. this must be a kelvin connection between ic and sense resistor. an undervolta ge lockout circuit (uvlo) prevents the switches from turning on while this input is less than its lockout threshold. 16, 21 3vouta, 3voutb 3.3vout. connected to 3.3v fet source. thes e are used to monitor the 3.3v output voltages for power-good status. 10, 27 12vouta, 12voutb 12vout. connected to 12v fet drain. these are used to monitor the 3.3v ou tput voltages for power-good status. 8, 29 12vsensea, 12vsenseb 12vmain low side of sense resistor connection. when eith er current limit threshold of the load current across the sense resistor = 50mv is reached, the related 12vga te pin is modulated to maintain a constant voltage across the sense resistor and thus a constant current into the load. if the 50mv threshold is exceeded for t flt , the isolation protection is tripped, and the gate pin fo r the affected supply?s extern al mosfet is immediately pulled high. this must be a kelvin connection between ic and sense resistor. 13, 24 3vsensea, 3vsenseb 3.3vmain low side of sense resistor connection. when eith er current limit threshold of the load current across the sense resistor = 50mv is reached, the related 3v gate pin is modulated to maintain a constant voltage across the sense resistor and thus a constant current into the load. if the 50mv threshold is exceeded for t flt , the isolation protection is tripped, and the gate pin fo r the affected supply?s extern al mosfet is immediately pulled low. this must be a kelvin connection between ic and sense resistor. 3, 34 12vgatea 12vgateb 12v gate drive outputs. each pin connects to the gate of an external p-channel mosfet. during power-up, the cgate and the cgs of the mosfets are connected to a 25 a current sink. this controls the value of dv/dt seen at the source of the mosfets. during current limit events, the voltage at this pin is adjusted to maintain constant current through the switch for a period of t flt . whenever an overcurrent, thermal shutdown, or input undervoltage fault condition occurs, the gate pin for the affected slot is immediately brought high. these pins are charged by an internal current source during power-down.
ISL6112 fn6456 rev 1.00 page 5 of 30 august 25, 2011 14, 23 3vgatea 3vgateb 3v gate drive outputs. each pin connects to the gate of an external n-channel mosfet. during power-up, th e cgate and the cgs of the mosfets are connected to a 25a current source. this controls the value of dv/dt seen at the source of the mosfets, and hence the curr ent flowing into the load capacitance. during current limit events, the voltage at this pin is adjusted to main tain constant current through the switch for a period of t flt . whenever an overcurrent, thermal shutdown, or input undervoltage fault condition occurs, the gate pin for the affected slot is immediately brought low. during power-down, these pins are discharged by an internal current source. 11, 26 vstbya, vstbyb 3.3v standby input voltage. required to su pport pci-express vaux output. a dditionally, the smbus logic and internal registers run off of v stby to ensure that the chip is accessible during standby modes. a uvlo circuit prevents turn-on of this supply until v stby rises above its uvlo threshold. both pins must be externally connected together at the ISL6112 controller. 15, 22 vauxa, vauxb 3.3vaux outputs to pci-express card slot s. these outputs connect the 3.3aux pin of the pci-express connectors to v stby via internal 400m ? mosfets. these outputs are 1a current limited and protected against short-circuit faults. 44, 43 ona, onb enable inputs. rising-edge triggered. used to enable or disable the maina and mainb (+3.3v and +12v) outputs. taking on low after a fault resets the +12v and/or +3.3v fault latches for the affected slot. tie these pins to gnd if using smi power control. also see pin descriptions for fault a and fault b. 45, 42 auxena, auxenb level sensitive auxiliary enable inputs. used to enable or disable the vaux outputs. taking auxen low afte r a fault resets the respective slot?s aux output fault latch. tie these pins to gnd if us ing smi power control. also see pin descriptions for fault a and fault b. 2, 35 cfiltera, cfilterb overcurrent timers. capacitors co nnected between these pins and gnd set the duration of cr tim . cr tim is the amount of time for which a slot remains in curr ent limit before its isolation protection is invoked. 6, 31 pwrgd a pwrgd b power-is-good outputs. open-drain, active-low. asserted when a slot has been commanded to turn on and has successfully begun delivering power to its respective +12v, +3.3v, and vaux outputs. each pin requires an external pull-up resistor to v stby . 1, 36 fault a, fault b fault outputs. open-drain, active-low. asserted whenever the isolation protection tr ips due to a fault condition (overcurrent, input undervoltage, over-temperature). each pin requires an external pull-up resistor to v stby . bringing the slot?s on pin low resets fault , if fault was asserted in response to a fault condition on one of the slot?s main outputs (+12v or +3.3v). fault is reset by bringing the slot?s auxen pin low if fault was asserted in response to a fault condit ion on the slot?s vaux output. if a fault condition occurred on both the main and vaux outputs of the same slot, then both on and auxen must be brought low to de-assert the fault output. 9, 28 force_on a force_on b enable inputs. active-low, level-sensitive. asserting a force_on input turns on all three of the respective slot?s outputs (+12v, +3.3v, and vaux) while specifical ly defeating all protections on those supplies. this explicitly includes all overcurrent and short-circuit pr otections, and on-chip thermal protection for the vaux supplies. additionally included are the uvlo pr otections for the +3.3v and +12vmain supplies. the force_on pins do not disable uvlo protection for the vaux supplies. these input pins are intended for diagnostic purposes only. asserting force_on causes the respective slot?s pwrgd and fault pins to enter their open-drain state. note that the smbus register se t continues to reflect the actual state of each slot?s supplies. there is a pair of register bits, accessible vi a the smbus, which can be set to disable (unconditionally de-assert) either or both of the force_on pins; see cntrl register bit d[2]. 4, 38 gpi_a0, gpi_b0 general purpose inputs. the states of thes e two inputs are available by re ading the common status register , bits [4:5]. if not used, connect each pin to gnd. 39, 40, 41 a2, a1, a0 smbus address select pins. connect to ground or leave open in order to program device smbus base address. these inputs have internal pull-up resistors to v stby . address programmed on rising v stby . 48 sda bidirectional smbus data line. 47 scl smbus clock input. 37 int interrupt output. open-drain, active-low output. asserted whenever a power fault is detected if the intmsk bit (cs register bit d[3]) is a logical ?0?. this output is cleared by performing an ?echo reset? to the appropriate fault bits in the stat or cs registers. this pin requires an external pull-up resistor to v stby . 17, 33, 46 gnd ic reference pins. connect together and tie direct ly to the system?s analog gnd plane directly at the device. 7, 18, 19, 20, 30 nc reserved. make no external connections to these pins. pin descriptions (continued) pin number pin name pin function
ISL6112 fn6456 rev 1.00 page 6 of 30 august 25, 2011 ordering information part number (note 2) part marking temp range ( c) package (pb-free) pkg. dwg. # ISL6112irza (notes 1, 3) ISL6112 irz -40 to +85 48 ld 7x7 qfn l48.7x7 ISL6112eval1z evaluation platform notes: 1. add ?-t*? suffix for tape and reel. please refer to tb347 for details on reel specifications. 2. these intersil pb-free plastic packaged products employ spec ial pb-free material sets, molding compounds/die attach materials , and 100% matte tin plate plus anneal (e3 termination finish , which is rohs compliant and compatible wi th both snpb and pb-free soldering opera tions). intersil pb-free products are msl classified at pb-fr ee peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jed ec j std-020. 3. for moisture sensitivity level (msl), please see device information page for ISL6112 . for more information on msl please see tech brief tb363 .
ISL6112 fn6456 rev 1.00 page 7 of 30 august 25, 2011 absolute maximum ratings ( note 4 ) thermal information 12vin, 12vsense, 12vout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +14.5v vstby, 3vin, 3vsense, 3vout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7v 12vgate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 12vi 3vgate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 12vi logic i/o . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5v to +5.5v vaux output current . . . . . . . . . . . . . . . . . . . . . . . . . short circuit protected esd rating human body model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2kv machine model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200v charged device model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1kv thermal resistance (typical) ? ja (c/w) ? jc (c/w) 48 ld 7x7 qfn package (notes 5, 6). . . . . 27 3 maximum junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150c maximum storage temperature range . . . . . . . . . . . . . .-65c to +150c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/ pbfree/pb-freereflow.asp operating conditions 12vmain supply voltage range. . . . . . . . . . . . . . . . . . . . . . . . +12v -10% 3.3vmain supply voltage range . . . . . . . . . . . . . . . . . . . . . . . +3.3v -10% auxi supply voltage range. . . . . . . . . . . . . . . . . . . . . . . . . . . . +3.3v -10% temperature range ( t a ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40c to +85c caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 4. all voltages are relative to gnd, unless otherwise specified. 5. ? ja is measured in free air with the componen t mounted on a high effective thermal conduc tivity test board with ?direct attach? fe atures. see tech brief tb379 . 6. for ? jc , the ?case temp? location is the center of the exposed metal pad on the package underside. electrical specifications 12vin = 12v, 3vin = 3.3v, vstby = 3.3v, t a = t j = -40c to +85c, unless otherwise noted. boldface limits apply over the operating temperature range, -40c to +85c. parameter symbol condition min (note 7) typ max (note 7) units power control and logic sections supply current icc12 hpi enabled or smi enabled with no load 0.9 1.5 ma icc3.3 0.1 0.2 ma iccstby 5 6 ma undervoltage lockout thresholds vuvlo(12v) 12vin increasing 8 9 10 v vuvlo(3v) 3vin increasing 2.1 2.5 2.75 v vuvlo(stby) vstby increasing 2.8 2.9 2.96 v undervoltage lockout hysteresis 12vin, 3vin vhysuv 180 mv undervoltage lockout hysteresis vstby vhysstby 50 mv power-good undervoltage thresholds vuvth(12v) 12vout decreasing 10.15 10.5 10.75 v vuvth(3v) 3vout decreasing 2.7 2.8 2.9 v vuvth(vaux) vaux decreasing 2.55 2.8 3 v power-good detect hysteresis vhyspg 30 mv 12vgate voltage vgate (12v) max. gate voltage when enabled 0 0.4 0.55 v 12vgate sink current igate(12vsink) start cycle 17 25 35 a 12vgate pull-up current (fault off) igate (12vpull- up) any fault condition (vdd ? vgate) = 2.5v 35 72 - ma 3vgate voltage vgate(3v) minimum gate voltage when enabled 12vin ? 0.3 12vin ? 0.2 12vin v 3vgate charge current igate (3vcharge) start cycle 17 25 35 a 3vgate sink current (fault off) igate(3vsink) any fault condition vgate = 2.5v 80 105 ma
ISL6112 fn6456 rev 1.00 page 8 of 30 august 25, 2011 cfilter overcurrent delay time pins 2 and 35 floating cfilter threshold voltage vfilter 1.20 1.25 1.30 v c filter charging current nominal current limit duration = c cfilter x 550k ifilter vxvin ? vx sense > vthilimit 2 2.5 3 a tfilter cfilter open 10 s current limit threshold voltages vthilimit vxin ? vxvsense 47.5 50 52.5 mv fast-trip threshold voltages vthfast vxvin ? vxvsense 85 100 115 mv xvsense input current isense 0.1 a low-level input voltage on, auxen, gpi, force_on , prsnt vil 0.8 v output low voltage fault , pwrgd vol iol = 3ma 0.4 v high-level input voltage on, auxen, gpi, force_on vih 2.1 5 v internal pull-ups to vstby rpull-up 40 50 k 12vin, 3vin input leakage current ilkg,off xvin vstby = +3.3v, 12vin = off; 3vin = off 0.5 1 a input leakage current, on, auxen, force_on iil -2 2 a off-state leakage current fault , pwrgd , gpi ilkg(off) gpi ilkg for these two pins measured with vaux off -2 2 a over-temperature shutdown and reset thresholds, with overcurrent on slot tov t j increasing, each slot 140 c t j decreasing, each slot 130 c over-temperature shutdown and reset thresholds, all other conditions (all outputs will latch off) t j increasing, each slot 160 c t j decreasing, each slot 150 c output mosfet resistance vaux mosfet r ds (aux) ids = 375ma 350 m off-state output offset voltage vaux voff(vaux) vaux = off 25 40 mv regulated current level ilim(aux) 0.8 1 1.2 a output discharge resistance rdis(12v) 12vout = 6.0v 1400 1850 rdis(3v) 3vout = 1.65v 140 180 rdis(vaux) 3vaux = 1.65v 350 400 12v current limit response time (see ?typical application diagram? on page 2). toff(12v) cgate = 25pf vin ? vsense = 140mv 1 2.1 s 3.3v current limit response time (see ?typical application diagram? on page 2). toff(3v) cgate = 25pf vin ? vsense = 140mv 0.3 1 s vaux current limit response time (see ?typical application diagram? on page 2). tsc vaux = 0v, vstby = +3.3v 2.5 s delay from main overcurrent to fault output tprop (12v fault or 3v fault) cfilter = 0 vin ? vsense = 140mv 1 s electrical specifications 12vin = 12v, 3vin = 3.3v, vstby = 3.3v, t a = t j = -40c to +85c, unless otherwise noted. boldface limits apply over the operating temperature range, -40c to +85c. (continued) parameter symbol condition min (note 7) typ max (note 7) units
ISL6112 fn6456 rev 1.00 page 9 of 30 august 25, 2011 delay from vaux overcurrent to fault output tprop (vauxfault) i lim(aux) to fault output cfilter = 0 vaux output grounded 1 s on, auxen, prsnt minimum pulse width tw 100 ns power-on reset time after vstby becomes valid tpor 250 s smbus timing scl (clock) period t1 2.5 s data in setup time to scl high t2 100 ns data out stable after scl low t3 300 ns data low setup time to scl low t4 100 ns data high hold time after scl high t5 100 ns note: 7. parameters with min and/or max limits are 100% tested at +25 c, unless otherwise specified. temperature limits established by characterization and are not production tested. electrical specifications 12vin = 12v, 3vin = 3.3v, vstby = 3.3v, t a = t j = -40c to +85c, unless otherwise noted. boldface limits apply over the operating temperature range, -40c to +85c. (continued) parameter symbol condition min (note 7) typ max (note 7) units
ISL6112 fn6456 rev 1.00 page 10 of 30 august 25, 2011 typical performance curves figure 3. iccstby current vs temperatur e figure 4. icc current vs temperature figure 5. current limit threshold voltage vs temperature figure 6. fast trip threshold voltage vs temperature figure 7. aux current limit vs temperature figure 8. aux r ds(on) vs temperature 4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 5.6 5.8 6.0 -60 -40 -20 0 20 40 60 80 100 120 temperature (c) iccstby (ma) smi iccstby hpi iccstby 0 0.2 0.4 0.6 0.8 1.0 -50 0 50 100 150 icc (ma) 3.3v icc 12v icc (hpi and smi) (hpi and smi) temperature (c) 47 48 49 50 51 52 53 -60 -40 -20 0 20 40 60 80 100 120 current limit vth (mv) temperature (c) 96 97 98 99 100 101 102 103 104 -60 -40 -20 0 20 40 60 80 100 120 woc threshold voltage (v) temperature (c) 800 850 900 950 1000 1050 1100 1150 1200 -60 -40 -20 0 20 40 60 80 100 120 aux current limit (ma) temperature (c) 200 220 240 260 280 300 320 340 360 380 400 -60 -40 -20 0 20 40 60 80 100 120 aux resistance (m ) iaux = 375ma temperature (c)
ISL6112 fn6456 rev 1.00 page 11 of 30 august 25, 2011 figure 9. 12main rising uvlo threshold voltage vs temperature figure 10. aux and 3.3main rising uvlo threshold voltage vs temperature figure 11. 12main power good threshold voltage vs temperature figure 12. aux and 3main power good threshold voltage vs temperature figure 13. ISL6112 gate turn-on current (abs) vs temperature figure 14. gate fault off current (abs) vs temperature typical performance curves (continued) 9.05 9.10 9.15 9.20 9.25 9.30 -60 -40 -20 0 20 40 60 80 100 120 12main uvlo rising (v) temperature (c) 1.5 1.7 1.9 2.1 2.3 2.5 2.7 2.9 3.1 -60 -40 -20 0 20 40 60 80 100 120 aux and 3main rising uvlo (v) aux 3main temperature (c) 10.38 10.40 10.42 10.44 10.46 10.48 10.50 10.52 10.54 -60 -40 -20 0 20 40 60 80 100 120 12main uv vth (v) temperature (c) 2.70 2.71 2.72 2.73 2.74 2.75 2.76 2.77 2.78 2.79 2.80 -60 -40 -20 0 20 40 60 80 100 120 aux and 3main uv vth (v) aux 3main temperature (c) 22.0 22.5 23.0 23.5 24.0 24.5 25.0 25.5 -60 -40 -20 0 20 40 60 80 100 120 turn-on curren t (a) 12vgate 3vgate temperature (c) 0 20 40 60 80 100 120 -60 -40 -20 0 20 40 60 80 100 120 gate fault off current (ma) 3gate 12gate temperature (c)
ISL6112 fn6456 rev 1.00 page 12 of 30 august 25, 2011 functional description the ISL6112 protects the power supplies in pci-express systems that utilize hot-pluggable add-in cards. this ic, together with two each of n-channel and p-channel mosfets, four current sense resistors, and a few external passive components, provides a compliant hot plug power control solution to any combination of two pci-express x1, x4, x8 or x16 slots. the ISL6112 primarily features start-up in-rush current protection, maximum current regulated (cr) levels for each of the main and aux outputs, and programmable cr duration so that both fault isolation protection and imperviousness to electrical transients are provided. the ISL6112 also offers input and output voltage supervisory functions and two operational system interfaces for implementation flexibility. in-rush current protection when any electronic circuitry is powered up, there is an in-rush of current due to the charging of bulk capacitance that resides across the circuit board supply pins. this transient in-rush current may cause the system supply voltages to temporarily droop out of regulation, causing data loss or system lock-up. the ISL6112 addresses these issues by limiti ng the in-rush currents to the pci-express add-in cards, thereby controlling the rate at which the load circuits turn on. see figures 17, 18, 19, 20, 21 and 22 for aux and main turn-on examples that illustrate the current limiting capabilities across a variety of compensation component values. main supply overcurrent protection for each of the 3vmain and 12vmain supplies, the current regulated (cr) levels are set by a sub ohm value sense resistor. the value for 12vmain is dependant on the size of the pci-express connector (x1, x4/x8 or x16) to be powered. the voltage across this resistor is compared to a 50mv internal reference, providing a nominal cr protection level that would be set above the maximum specified slot limits. the 3.3vmain supply can use a 15m ? sense resistor compared to a 50mv reference to provide a nominal regulated current limit of 3.3a, as this supply has a common 3a maximum across all slot sizes. for both main supplies, there is a way overcurrent (woc) shutdown protocol that is without a cr duration. woc is invoked if the load current causes the rsense voltage to be >100mv (see figures 23 and 24). vaux supply overcurrent protection the vaux load current is internal ly monitored and controlled via an internal power fet. this fet has a typical r ds(on) of 320m at a vaux current of 375ma to mi nimize distribution losses to typically <100mv through the ic. using active monitoring and control, the ISL6112 provides nominal limiting to ~1000ma of load current across the temperature range and for various loading conditions. see figures 17, 25 and 26 for examples of this performance. current regulation (cr) duration the cr duration for each slot is set by an external capacitor between the associated cfilter pin and ground. this feature masks current transients and overcurrents prior to supply turn-off. once the cr duration has expired, the ic quickly turns off the associated main outputs via its external fets or the failed aux output, unloading the faulte d load card from the supply voltage rails. uvlo, power-good, and fault the ISL6112 incorporates undervoltage lock-out (uvlo) protections on each of the four main vin and two vstby supplies to prevent operation during a br own-out condition. likewise, on the outputs are minimum voltag e compliances that must be satisfied for the power-good outp ut, pwrgd, to be asserted. there is some hysteresis on the uvlo levels as the voltage on vin decreases to ensure ic operat ion below the minimum operating supply standards. the fault output is asserted (low) whenever there is an oc, ot or uv condition. the fault is cleared once the appropriate enable is deasserted. operational system interfaces the ISL6112 employs two system interfaces: the hardware hot-plug interface (hpi) and the system management interface (smi). the hpi i/o includes on, auxen, fault and pwrgd . the smi i/o consists of sda, scl, and int , the signals of which conform to the levels and timing of the smbus specification (see figure 15. filter charge current vs temperature f igure 16. filter threshold voltage vs temperature typical performance curves (continued) 2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3.0 -60 -40 -20 0 20 40 60 80 100 120 filter current (a) temperature (c) 1.20 1.22 1.24 1.26 1.28 1.30 -60 -40 -20 0 20 40 60 80 100 120 filter threshold (v) temperature (c)
ISL6112 fn6456 rev 1.00 page 13 of 30 august 25, 2011 ?smi-only control applications? on page 18). the ISL6112 can be operated exclusively from either the smi or hpi, or can employ the hpl for power control while continuing to use the smi for access to all but the power control registers. in addition to the basic power control features of the ISL6112 accessible by the hpi, the smi gives the host access to the following information from the part: ? fault conditions occurring on ea ch supply. these faults include overcurrent, over-temperature and undervoltage. ? gpi pin status when using the system. when using the smi for power cont rol, the hpi must not be used. conversely, when using the hpi fo r power control, power control commands must not be executed over the smi bus. all other register accesses via the smi bus remain permissible while in hpi control mode. when using smi exclus ively, the hpi input pins (on, auxen, and force_on ) should be configured as shown in figure 27 (disabling hpi when smi contro l is used). this configuration safeguards the power slots if the smbus communication link is disconnected for any reason. when using hpi exclusively, the smbus (or smi) will be inactive if the input pins (sda, scl, a0, a1, and a2) are configured as shown in figure 27. figure 17. vaux turn-on r load = 10 , c load = 100f figure 18. 12vmain start-up r load = 10 , c load = 470f figure 19. 3vmain start-up r load = 2 , c load = 470f figure 20. 12vmain start-up r load = 10 , c load = 470f vaux iaux auxen vaux iaux auxen 12v out 12v gate c gd = 6800pf 12i out c filter c gs = 22nf 3v out 3v gate 3i out c filter c gate = 22nf c filter responding to unshown main supply 12v out 12v gate c gd = 6800pf 12i out c filter c gs = 2200pf
ISL6112 fn6456 rev 1.00 page 14 of 30 august 25, 2011 figure 21. 3vmain start-up r load = 2 , c load = 470f figure 22. 12vmain start-up r load = 10 , c load = 470f figure 23. 12vmain woc shut-down figure 24. 3vmain woc shut-down figure 25. vaux oc regulation and shut-down figure 26. vaux woc regulation and shut-down 3v gate 3v out 3i out c filter c gate = 2200pf c filter responding to unshown main supply 12v out 12v gate c gd = 9800pf 12i out c filter c gs = 2200pf 12i out 12v gate c filter 12v out 3v gate c filter 3i out 3v out c filter vaux iaux c filter vaux iaux
ISL6112 fn6456 rev 1.00 page 15 of 30 august 25, 2011 ISL6112 bias, power-on reset, and power cycling the ISL6112 uses vstby as the only supply source. vstby is required for proper operatio n of the ISL6112 smbus and registers and must be applied at all times. a power-on-reset (por) cycle is initiated after vstb y rises above its uvlo threshold and remains satisfied for 250s. all internal registers are cleared after por. if vstby is recycled, the ISL6112 enters a new por cycle. vstby must be the first supply voltage applied, followed by the main supply inputs of 12vi n and 3vin. the smbus is ready for access at the end of the po r cycle (250s after vstby is valid). during t por , all outputs remain off. enabling the vaux outputs upon asserting an auxen input, the related internal power switch turns on, connecting the nominally 3.3v vstby supply to its vaux load. the turn-on is slew rate limited and invokes the current regulation feature so as not to droop the supply due to in-rush current load. figure 17 illustrates the vaux turn-on performance into a 10 ? , 100f load. standby mode standby mode is entered when one or more of the main supply inputs (12vin and/or 3vin) is either absent, below its respective uvlo threshold, or off. the ISL6112 also has 3.3v auxiliary outputs (vauxa and vauxb), sati sfying an optional pci-express requirement. these outputs are fed from the vstby input pins. they are independent of the main outputs and are controlled by the auxen input pins or via their respective bits in the control registers. should the main supply inputs fall below their respective uvlo thresholds, vaux still functions, as long as vstby is compliant. prior to st andby mode, ona and onb (or the control register maina and ma inb bits) inputs must be deasserted, or the ISL6112 asserts its fault outputs. if an figure 27. i/o configuration for disabling hpi/smi control figure 28. 12vmain cr and shut-down figure 29. 3vmain cr and shut-down disabling smi when hpi control is used disabling hpi when smi control is used scl sda int# a2 a1 a0 100k 100k 100k v stby int foron#_a foron#_b auxena auxenb ona onb 100k 100k v stby 9 28 45 42 44 43 c filter 12v gate 12i out 12v out c filter 3v out 3i out 3v gate
ISL6112 fn6456 rev 1.00 page 16 of 30 august 25, 2011 undervoltage condition on either of the main supply inputs is detected, int also asserts, if interrupts are enabled. enabling the main gate outputs when a slot's main supplies are off, the 12vgate pin is held high with an internal pull-up to the 12vin voltage. similarly, the 3vgate pin is internally held low to gnd. when the main supplies of the ISL6112 are enabled by asserting on, the related 3vgate and 12vgate pins are each connected to a constant current supply. for the 3vgate pin, this supply is nominally a 25a current source. for the 12vgate pin, the supply is nominally a -25a current sink. th e 3vgate is charged up to the 12vin voltage, while the 12gate is pulled down to gnd, for maximum enhancement of the n-channel and p-channel fets, respectively. estimating in-rush current and v out slew rate at start-up the expected in-rush current can be estimated by using equation 1: where 25a is the gate pin charge current, and c load is the load capacitance. c gate is the total gate capacitance, including c iss of the external mosfet and any external capacitance connected from the gate output pi n to the gate reference, gnd, or source. an estimate for the output slew rate of 3.3v outputs and 12v outputs, where there is little or no external 12vgate output capacitors, can be determined from equation 2: where i lim = 50mv/r sense and c load is the load capacitance. as a consequence, the cr duration, t filter, must be programmed to exceed the time it takes to fully charge the output load to the input rail voltage level. main outputs (start-up delay and slew-rate control) the 3.3v outputs act as source followers. in this mode of operation, v source = [v gate ? v th(on) ] until the associated output reaches 3.3v. the voltage on the gate of the mosfet continues to rise until it reac hes 12v, which ensures minimum r ds(on) . for the 12v outputs, the mosfet can be optionally configured as a miller integrator by adding a c gd capacitor connected between the mosfet's gate and drain to adjust the vout ramp time. in this configur ation, the feedback action from drain to gate of the mosfet caus es the voltage at the drain of the mosfet to slew in a linear fashion at a rate estimated by equation 3: table 1 approximates the output slew-rate for various values of c gate when start-up is dominated by gate capacitance (external c gate from gate pin to ground, plus c gs of the external mosfet for the 3.3v rail and c gd for the 12v rail). note that all of these performance estimates are useful only for first-order time and loading expectations, because they do not look at other significant loading factors. figures 18, 19, 20, 21 and 22 illustrate empirically the discussed turn-on performance with the noted loading and compensation conditions. notice the degree of control ov er the in-rush current and the gate ramp rate as the values are changed, which provides for highly customizable tu rn-on characteristics. in some scope shots, although the c filter shows ramping in the absence of excessive displayed loading current, c filter is responding to the other main supply current that is not displayed. all scope shots were taken from the ISL6112eval1z, with any component changes noted. current regulation (cr) function the ISL6112 provides a current re gulation and limiting function that protects the input voltage supplies against excessive loads, including short circuits. when th e current from any slot?s main outputs exceeds the current limit threshold (i lim = 50mv/r sense ) for a duration greater than t filter , the isolation protection is tripped, and both related main su pplies are shut off, as shown in figures 28 and 29. should the lo ad current cause a main output v sense to exceed v thfast , the output is immediately shut off, with no t filter delay, as shown in figures 28 and 29. the vaux outputs have a differen t isolation protection function. the vaux isolation circuit does not incorporate a fast-trip detector; instead, they regulate the output current into a fault to avoid exceeding their operating current limit. the protection circuit trips due to an overcurrent on vaux when the programmable cr duration timer, t filter , expires. this use of the t filter timer prevents the circuit fr om tripping prematurely due to brief current transients. see figures 25 and 26 for illustrations of the vaux protection performa nce into a slight oc and more severe oc condition, respectively. the ISL6112 aux current control responds proportionally to the severity of the oc condition, resulting in faster vaux pull-down and current regulation until t filter has expired. following a fault condition, the outputs can be turned on again (1) via the on inputs if the fault occurred on one of the main outputs), (2) via the auxen inputs if the fault occurred on the aux outputs, or (3) by cycling both on and auxen if faults occurred on (eq. 1) i in rush C nominally 25 ? a c load c gate ----------------- ?? ?? ?? = ----------------- = ? a c gd -------------- - = .
ISL6112 fn6456 rev 1.00 page 17 of 30 august 25, 2011 both the main and aux outputs. a fault condition can alternatively be cleared under smi control of the enable bits in the cntrl registers (see ?contr ol register bits d[1:0]? on page 21). when the circuit protection trips, fault is asserted if the outputs were enabled through the hpi inputs. if smi is enabled, int is asserted (unless interrupts are masked). note that int is deasserted by writing a logic 1 back into the respective fault bit positions in the stat register or the ?common status register (cs) 8-bi ts, read/write? on page 24. the ISL6112 current regulation duration (t filter ) is individually set for each slot by an external capacitor at the cfilter pin to gnd. once the cr mode is entered, the external cap is charged with a 2.5a current source to 1.25v. once this threshold has been reached, the ic turns off only the related faulted outputs [either both main (external fets ) outputs or aux (internal fet)] and sets the fault output low. for a desired t filter , the value for c filter is given by equation 4: where 500k ?? is the nominal ? v filter/nominal i filter and where t filter is the desired response time, with the values for i filter and v filter being found in the ?electrical specifications table? on page 7. see table 2 for nominal t filter times for given c filter cap values. because the ISL6112 has its cr feature invoked as it turns on the fets into the load, t filter consideration is minimal. a maximum bulk capacitance is specified for each supported power level, and it must be charged at the cr limit. in-rush current time must be considered when determining t filter duration. power-down cycle when a slot is turned off under either hpi or smi control, internal discharge fets connected to the output load provide a discharge path for load capacitance connected to the part?s outputs. these fets ensure the outputs are pulled to gnd. this is a compliance requirement if a replacement add-in card is inserted into the slot. thermal shutdown the internal vaux mosfets are protected against damage not only by current limiting, but by a dual-mode over-temperature protection scheme as well. each slot controller on the ISL6112 is thermally isolated from the other. should an overcurrent condition raise the junction temperature of one slot?s controller and pass elements to +140c, all ou tputs for that slot (including vaux) are shut off, and the slot?s fault output is asserted. the other slot?s operating condition remains unaffected. however, should the ISL6112 die temperature exceed +160c, both slots (all outputs, including vauxa and vauxb) are shut off, whether or not a current limit condition ex ists. a +160c over-temperature condition additionally sets the ov er-temperature bit (ot_int) in the common status register (see ?common status register (cs) 8-bits, read/write? on page 24). pwrgd outputs the ISL6112 has two pwrgd outputs; one for each slot. these open-drain, active-low outputs requ ire an external pull-up resistor to v stby . each output is asserted when a slot has been enabled and has successfully begun delive ring power to its respective +12v, +3.3v, and vaux outputs. an equivalent logic diagram for pwrgd is shown in figure 30. force_on inputs the level-sensitive, active-low force_on inputs are provided to facilitate design or debugging of systems using the ISL6112. asserting force_on turns on all three of the respective slot?s outputs (12main, 3main, and vaux), while specifically defeating all overcurrent and short circuit protections and on-chip thermal protection for the vaux supplies. additionally, asserting force_on disables all input and output uvlo protections, with the exception of the vstby input, uvlo. asserting force_on causes the slot pwrgd and fault outputs to enter the open-drain state. additionally, there are two smbus accessible register bits (see control register bit d[2] in tables 5 and 7) that can be set to disable the corresponding slot?s force_on pins. this allows system software to prevent these hardware overrides from being inadvertently activated during normal use. when not used, each force_on pin can be connected to v stby by using an external pull-up resistor, or it can simply be shorted to vstby. general purpose input (gpi) pins two pins on the ISL6112 are available for use as gpi pins. the logic state of each of these pins can be determined by polling bits [4:5] of the common status register. both of these inputs are compliant to 3.3v. if gpi is not used, each input must be connected to gnd. hot-plug interface (hpi) after the input supplies are above their respective uvlo thresholds, the hot-plug interface can be used for power control by enabling the control input pins (auxen and on) for each slot. for the ISL6112 to turn on the vaux supply for either slot, the auxen control must be enabled after the power-on-reset delay, t por (typically, 250s), has elapsed. system management interface (smi) the ISL6112 system management interface (smi) uses the read_byte and write_byte subsets of the smbus protocols to communicate with its host via the smi bus. the int output signals the controlling processor that one or more events need attention, if an interrupt-driven architecture is used. note that the ISL6112 does not participate in the smbus alert response address (ara) portion of the smbus protocol. table 2. nominal t filter duration c filter capacitance (f) time (ms) open 0.01 0.01 5 0.022 11 0.047 24 0.1 50 note: nominal cr_dur = c filter cap ( ? f) * 500k ? . c filter nominal t filter 500k ? ----------------------------------------- - = (eq. 4)
ISL6112 fn6456 rev 1.00 page 18 of 30 august 25, 2011 fault reporting and interrupt generation smi-only control applications for applications in which the isl6 112 is controlled only by smi, on and auxen are connected to gnd, and the force_on pins are either shorted or are connected to v stby as shown in figure 27. in these cases, the ISL6112 fault outputs and status register bit d[7] (fault) are not activated, because fault status is determined by polling status register bits d[4], d[2], d[0] and cs (common status) register bits d[2:1]. individual fault bits in the status and cs registers are asserted after por, when: ?either or both cntrl register bits d[1:0] are asserted, and ? 12vin, 3vin, or vstby input voltage is lower than its respective ulvo threshold, or ? the fast oc circuit isolatio n protection has tripped, or ? the slow oc circuit isolation protection has tripped and its filter time-out has expired, or ? the slow oc circuit isolation protection has tripped and slot die temperature > +140c, or ? the ISL6112 global die temperature > +160c once asserted, to clear any one or all status register bits d[4], d[2], d[0] or cs register bits d[2], d[1], a software subroutine can perform an ?echo reset? in which a logical ?1? is written back to those register bit locations that have indicated a fault. this method of ?echo reset? allows data to be retained in the status and/or cs registers until such time as the system is prepared to operate on that data. the ISL6112 can operate in interrupt mode or polled mode. for interrupt-mode operation, the open-drain, active-low int output signal is activated after por if the intmsk bit (cs register bit d[3]) has been reset to logical ?0?. once activated, the int output is asserted by any one of the fault conditions previously listed. it is deasserted when one or all status register bits d[4], d[2], d[0] or cs register bits d[2], d[1] are reset upon the execution of an smbus ?echo re set? write_byte cycle. for polled-mode operation, the intmsk bit should be set to logical ?1,? thereby inhibiting int output pin operation. for smi control applications in which the force_on inputs are needed for diagnostic purposes, the force_on inputs must be enabled; that is, cntrl register bi t d[2] should read logical ?0.? once force_on inputs are asserted, al l output voltages are present with all circuit protection features disabled, including over-temperature protection on vaux outputs. to inhibit force_on operation, a logical ?1? is written to the cntrl register bit d[2] locations. hpi-only control applications for applications in which the isl6 112 is controlled only by hpi, smbus signals scl, sda, and int are connected to v stby as shown in figure 27. in this configuration, the ISL6112 fault outputs are activated after po r and become asserted when: either or both external on and auxen input signals are asserted, and ? 12vin, 3vin, or vstby input voltage is lower than its respective ulvo threshold, or ? the fast oc circuit isolatio n protection has tripped, or ? the slow oc circuit isolation protection has tripped and its filter time-out has expired, or ? the slow oc circuit isolation protection has tripped and slot die temperature > +140c, or ? the ISL6112 global die temperature > +160c. to clear fault outputs, once asserted, either or both on and auxen input signals must be deasserted. (see fault pin in ?pin descriptions? table on page 4 for additional information.) if the force_on inputs are used for diagnostic purposes, both the fault and pwrgd outputs are deasserted after the force_on inputs are asserted. serial port operation the ISL6112 uses standard smbus write_byte and read_byte operations for communication with its host. the smbus write_byte operation involves sending the device?s target address, with the r/w bit (lsb) set to the low (write) state, followed by a command byte and a data byte. the smbus read_byte operation is similar, but it is a composite write and read operation. the host first se nds the device?s target address, followed by the command byte, as in a write operation. a new vstby pwrgd auxen (1) on (1) force_on (1) (1) external pin (2) cntrl register bit d[0] (3) internal flag (4) cntrl register bit d[1] (5) cntrl register bit d[2] main (4) vaux (2) 3vaux_uv (3) force_en (5) 12vout_uv (3) 3vout_uv (3) figure 30. pwrgd logic diagram
ISL6112 fn6456 rev 1.00 page 19 of 30 august 25, 2011 ?start? bit must then be sent to the ISL6112, followed by a repeat of the device address, with the r/w bit set to the high (read) state. the data to be read from the part may then be clocked out. the exception to this rule is that, if the location latched in the pointer register from the last write operation is known to be correct (i.e., points to the desi red register within the ISL6112), the ?receive_byte? procedure may be used. to perform a receive_byte operation, the host sends an address byte to select the target ISL6112, with the r/w bit set to the high (read) state, and then retrieves the data byte. figures 33, 34 and 35 show the formats for these data read and data write procedures. the command register is eight bits (one byte) wide. this byte carries the address of the ISL6112 register to be operated upon. command byte values corresponding to the ISL6112 register addresses are shown in table 4. command byte values other than 0000 0xxx b = 00 h ? 07 h are reserved and should not be used. ISL6112 smbus address configuration the ISL6112 responds to its ow n unique smbus address, which is assigned using a2, a1, and a0. these represent the three least significant bits (lsb) of its 7-bit address, as shown in table 3. these address bits are assigned only during power-up of the vstby supply input. these address bits allow up to eight ISL6112 devices in a single sy stem. these pins are either grounded or left unconnected to specify a logical 0 or logical 1, respectively. a pin designated as a logical 1 may also be pulled up to vstby. table 3. ISL6112 smbus addressing inputs ISL6112 device address a2 a1 a0 binary hex 0 0 0 1000 000x*b 80h 0 0 1 1000 001xb 82h 0 1 0 1000 010xb 84h 0 1 1 1000 011xb 86h 1 0 0 1000 100xb 88h 1 0 1 1000 101xb 8ah 1 1 0 1000 110xb 8ch 1 1 1 1000 111xb 8eh * where x = ?1? for read and ?0? for write
ISL6112 fn6456 rev 1.00 page 20 of 30 august 25, 2011 timing diagrams figure 31. smbus timing figure 32. hot-plug interface operation figure 33. write_byte protocol t 4 scl sda data in sda data out t 2 t 5 t 3 int * fault _ i3vout 3vout i aux_out vaux_out auxen 0 vih vih vil vih ilim(3v) isteady-state on 0 0 0 0 0 0 0 vih vil +3.3v tpor vstby uvlo tflt tflt ilim(aux) isteady-state 0 0 ** * int de-asserted by software 12vout pwrgd _ s1000a2a1a00a00000xxxa d4 d5 d6 d3 d2 d1 d0 d7 a p ISL6112 device address data clk command byte to ISL6112 data byte to ISL6112 start r/w = write acknowledge acknowledge acknowledge master to device transfer, i.e., data driven by master. device to master transfer, i.e., data driven by device.
ISL6112 fn6456 rev 1.00 page 21 of 30 august 25, 2011 ISL6112 register set and programmer?s model detailed register descriptions control register, slot a (c ntrla) 8-bits, read/write figure 34. read_byte protocol figure 35. receive_byte protocol table 4. ISL6112 register addresses target register command byte value power-on default label description read write cntrla control register slot a 02h 02h 00h cntrlb control register slot b 03h 03h 00h stata slot a status 04h 04h 00h statb slot b status 05h 05h 00h cs common status register 06h 06h xxxx 0000b reserved reserved/do not use 07h - ffh 07h - ffh undefined table 5. control register, slot a (cntrla) d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0] read-only read-only read-only read-only read -only read/write read/write read/write auxapg mainapg reserved reserved reserved force _a enable maina vauxa timing diagrams (continued) s1000a2a1a0 a2a1a0 0a00000xxxas1 0 1 00 d4 d5 d6 d3 d2 d1 d0 ad7 /a p ISL6112 device address data clk command byte to ISL6112 ISL6112 device address data read from ISL6112 start start r/w = write r/w = read acknowledge acknowledge acknowledge not acknowledge master to device transfer, i.e., data driven by master. device to master transfer, i.e., data driven by device. s1000a2a1a01a d4 d5 d6 d3 d2 d1 d0 d7 /a p ISL6112 device address data clk byte read from ISL6112 start stop r/w = read acknowledge not acknowledge master to device transfer, i.e., data driven by master. device to master transfer, i.e., data driven by device. bit(s) function operation auxapg aux output power-good status, slot a 1 = power-is-good (vauxa output is above its uvlo threshold) mainapg main output power-good status, slot a 1 = power-is-good (maina outputs are above their uvlo thresholds) d[5] reserved always read as zero d[4] reserved always read as zero
ISL6112 fn6456 rev 1.00 page 22 of 30 august 25, 2011 status register slot a (statusa) 8-bits, read-only d[3] reserved always read as zero force _a enable allows or inhibits the operation of the force_on a input pin 0 = force_on a is enabled 1 = force_on a is disabled maina main enable control, slot a 0 = off, 1 = on vauxa vaux enable control, slot a 0 = off, 1 = on power-up default value: 0000 0000 b = 00 h read command_byte value (r/w ): 0000 0010 b = 02 h the power-up default value is 00 h . slot is disabled upon power-up; i.e., all supply outputs are off. notes: 8. the state of the pwrgd a pin is the logical and of the values of the au xapg and the mainapg bits, except when force_on a is asserted. if force_on a is asserted (the pin is pulled low), and force _aenable is set to a logic zero, the pwrgd a pin will be unconditionally forced to its open-drain (?power not good?) state. 9. the values of the mainapg and auxapg re gister bits are not affected by force_on a, but will instead continue to read as high if power is ?good,? and as low if the conditions that indicate power is good are not met. bit(s) function operation table 6. status register, slot a (stata) d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0] read-only read-only read-only read/write read-only read/write read-only read/write faulta maina vauxa vauxaf reserved 12vaf reserved 3vaf bit(s) function operation faulta fault status - slot a 1 = fault pin asserted (fault a pin is low); 0 = fault pin deasserted (fault a pin is high). see notes 10, 11, and 12. maina main enable status - slot a represents the actual state (on/off) of the two main power outputs for slot a (+12v and +3.3v). 1 = main power on; 0 = main power off vauxa vaux enable status - slot a represents the actual state (on/off) of the auxiliary power output for slot a. 1 = aux power on; 0 = aux power off vauxaf overcurrent fault: vauxa supply 1 = fault; 0 = no fault d[3] reserved always read as zero 12vaf overcurrent fault: +12v supply 1 = fault; 0 = no fault d[1] reserved always read as zero 3vaf overcurrent fault: 3.3v supply 1 = fault; 0 = no fault
ISL6112 fn6456 rev 1.00 page 23 of 30 august 25, 2011 control register, slot b (c ntrlb) 8-bits, read/write power-up default value: 0000 0000 b = 00 h command_byte value (r/w): 0000 0100 b = 04 h the power-up default value is 00 h . both slots are disabled upon power-up; i.e., all supply output s are off. in response to an overcurrent fault condition, writing a logical 1 back into the active (or set) bit position will clear the bit and deassert int . the status of the fault a pin is not affected by reading the status register or by clearing active status bits. notes: 10. if faulta has been set by an overcurrent condition on one or more of the main outputs, the on a input must go low to reset fa ulta. if faulta has been set by a vauxa overcurrent event, the auxena input must go low to reset faulta. if an overcurrent has occurred on both a m ain output and the vaux output of slot a, both ona and auxena of the slot must go low to reset faulta. 11. neither the faulta bits nor the fault a pins are active when the ISL6112 power paths are controlled by smi. when using smi power path control, auxena and ona pins for that slot must be tied to gnd. 12. if force_on a is asserted (low), the fault a pin will be unconditionally forced to its open-drain state. note that the value in the faulta register bit is not affected by force_on a. it will instead continue to read as a high if no faults ar e present on slot a, and as a low if any fault conditions exist that would disable slot a if force_on a was not asserted. table 7. control register, slot b (cntrlb) d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0] read-only read-only read-only read-only read-only read/wri te read/write read/write auxbpg mainbpg reserved reserved reserved force _b enable mainb vauxb bit(s) function operation bit(s) function operation auxbpg aux output power-good status, slot b 1 = power- is-good (vauxb output is above its uvlo threshold) mainbpg main output power-good status, slot b 1 = power-is-good (mainb outputs are above their uvlo thresholds) d[5] reserved always read as zero d[4] reserved always read as zero d[3] reserved always read as zero force _b enable allows or inhibits the operation of the force_on b input pin 0 = force_on b is enabled 1 = force_on b is disabled mainb main enable control, slot b 0 = off, 1 = on vauxb vaux enable control, slot b 0 = off, 1 = on power-up default value: 0000 0000 b = 00 h command_byte value (r/w): 0000 0011 b = 03 h the power-up default value is 00 h . slot is disabled upon power-up; i.e., all supply outputs are off. notes: 13. the state of the pwrgd b pin is the logical and of the values of the auxbpg and mainbpg bits, except when force_on b is asserted. if force_on b is asserted (the pin is pulled low), and force _benable is set to a logic zero, the pwrgd b pin will be unconditionally forced to its open-drain (?power not good?) state. 14. the values of the mainbpg and auxbpg register bits are not affected by force_on b, but will instead continue to read as high if power is ?good,? and as low if the conditions, which indi cate that power is good, are not met.
ISL6112 fn6456 rev 1.00 page 24 of 30 august 25, 2011 status register slot b (statb) 8-bits, read-only common status register (cs) 8-bits, read/write table 8. status register, slot b (statb) d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0] read-only read-only read-only read/write read-only read/w rite read-only read/write faultb mainb vauxb vauxbf reserved 12vbf reserved 3vbf bit(s) function operation faultb fault pin status - slot b 1 = fault pin asserted (fault b pin is low); 0 = fault pin deasserted (fault b pin is high). see notes 15, 16, and 17. mainb main enable status - slot b represents the actual state (on/off) of the four main power outputs for slot b (+12v and +3.3v): 1 = main power on 0 = main power off vauxb vaux enable status - slot b represents th e actual state (on/off) of the auxiliary power output for slot b: 1 = aux power on 0 = aux power off vauxbf overcurrent fault: vauxb supply 1 = fault; 0 = no fault d[3] reserved always read as zero 12vbf overcurrent fault: +12v supply 1 = fault; 0 = no fault d[1] reserved always read as zero 3vbf over current fault: 3.3v supply 1 = fault; 0 = no fault power-up default value: 0000 0000h = 00h command_byte value (r/w): 0000 0101 b = 05 h the power-up default value is 00 h . both slots are disabled upon power-up; i.e., all supply output s are off. in response to an overcurrent fault condition, writing a logical 1 back into the active (or set) bit position will clear the bit and deassert int . the status of the fault b pin is not affected by reading the status register or by clearing active status bits. notes: 15. if faultb has been set by an overcurrent condition on one or more of the main outputs, the onb input must go low to reset fa ultb. if faultb has been set by a vauxb overcurrent event, the auxenb input must go low to reset faultb. if an overcurrent has occurred on both a main output and the vaux output of slot b, both onb and auxenb of the slot must go low to reset faultb. 16. neither the faultb bits nor the fault b pins are active when the ISL6112 power paths are cont rolled by smi. when using smi power path control, the auxenb and onb pins for that slot must be tied to gnd. 17. if force_on b is asserted (low), the fault b pin will be unconditionally forced to its open-drain state. note that the value in the faultb register bit is not affected by force_on b, but will instead continue to read as a high if no faults ar e present on slot b, and as a lo w if any fault conditions exist that would disable slot b if force_on b was not asserted. table 9. common status register (cs) d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0] read-write read-write read-o nly read-only read-write read -write read-write read-only reserved reserved gpi_b0 gpi_a0 intmsk uv_int ot_int reserved bit(s) function operation d[7] reserved always read as zero d[6] reserved always read as zero
ISL6112 fn6456 rev 1.00 page 25 of 30 august 25, 2011 pci-express application recommendations for each of the 3.3vmain and +1 2vmain supplies, the cr level is set by an external sense resistor value. this value depends on the maximum power specified for the pci-express connector and the application (x1, 10w or 25w; x4, x8, 25w; x16, 25w or 75w; and x16 graphics -atx, 150w). the power rating is a combination of the main and the optional auxiliary supplies. the sense resistor is a low ohmic, standard value current sense resistor (one for each slot). the voltage across this resistor is compared to a 50mv reference. the 3.3vmain supply is rated for 3a maximum across all slots, rega rdless of size and power. the use of a 15m ? sense resistor compared to the 50mv reference provides a nominal cr of 3.3a, or 11% higher than the 3a maximum specification. on the 12vmain, for a 10w connector, a 75m ? sense resistor provides a nominal cr level of 0.66a, 32% above the 0.5a maximum specification. for a 25w connector, a 20m ? sense resistor provides a nominal cr level of 2.5a, which is 19% above the 2.1a maximum specification. for a 75w connector, an 8m ? sense resistor provides a nominal cr level of 6.25a, or 14% above the 5.5a maximum specification. the x16 graphics-atx 150w card is a special case. the 150w is provided by two slots, each providing up to a maximum of 75w from the 12vmain, as this type of card does not consume 3.3vmain or aux supply power. for each of the slots, a 7m ? sense resistor provides a nominal cr level of 7.1a, which is 14% above the 6.25a maximum specification. the ISL6112 provides a best-in-class 5% current regulation threshold specification over temp erature for the main supplies. this is the highest accuracy and lo west variability for this critical parameter. table 10 shows recommended 12vmain sense resistor values for particular power levels. providing a nominal cr protection level above the maximum specified limits of the card ensure s that the card is able to draw its maximum specified loads. it also ensures enough headroom before a regulated current limiter is invoked to protect against transients and other events. this headroom margin can be adjusted up or down by using different sense resistor values. gpi_b0 general purpose input 0, slot b state of gpi_b0 pin gpi_a0 general purpose input 0, slot a state of gpi_a0 pin intmsk interrupt mask 0 = int generation is enabled 1 = int generation is disabled the ISL6112 does not participate in the smbus alert response address (ara) protocol. uv_int undervoltage interrupt 0 = no uvlo fault 1 = uvlo fault set whenever a circuit isolation protection fault condition occurs as a result of an undervoltage lockout condition on one of the main supply inputs. this bit is only set if a uvlo condition occurs while the on pin is asserted or the main control bits are set. ot_int over-temperature interrupt 0 = die temp < +160c. 1 = fault: die temp > +160c. set if a fault occurs as a result of the ISL6112 die temperature exceeding +160c. d[0] reserved undefined power-up default value: 00000000 b = 00 h command_byte value (r/w): 00000110 b = 06 h note: to reset the ot_int and uv_int fault bits, a logical 1 must be written back to these bits. bit(s) function operation table 10. nominal current regulation level 12vmain r sense (m ) 12vmain cr (a) pci-e add-in board power level supported (w) 75 0.7 10 20 2.5 25 86.2 75 7 7 150 note: cr level = vth ilimit /r sense .
ISL6112 fn6456 rev 1.00 page 26 of 30 august 25, 2011 using the ISL6112eval1z platform the primary ISL6112 evaluation platform is shown photographically in figure 36 and schematically on page 28. this evaluation board highlights a pc b layout that confines all necessary active and passive components in an area measuring 12mmx55mm. this width is smaller than the specified pci-express socket-to-socket sp acing, allowing for intimate co-location of the load power control and the load itself. around the central highlighted layout are numerous labeled test points and configuration jumpers where there are node names such as ao(l/r ). the pin name outside the parentheses relates to the ISL6112. the isl6113 and isl6114 also use this evaluation platform, as all three parts have a common pinout for the common pin functions. the pi n names in parentheses are for the isl6113 and isl6114. the specific evaluation board ordered and received will reflect the part number in the area below the intersil logo, either by label or silk-screened lettering. for pins that are not common across the ISL6112, isl6113, and isl6114, there is a matrix detailing the differences in the bottom left corner. the ISL6112eval1z is provided in hpi mode, with the clock shorted to ground. the evaluation platform is to be biased through the six banana jacks: turn on the vstby supply first, and then the other main supplies, in any order. with appropriate signaling to the auxen and on inputs, the user should see turn-on waveforms. external current loading must be added to demonstrate oc and woc response performance. the scl and sda inputs in th e top right quadrant of the evaluation board can be used to demonstrate smi operation. the board?s default address is config ured as ?000? via three jumpers located on the right side of the board and labeled a0, a1, and a2. the hpi inputs must be disabled as shown in figure 27. if additional software is needed to configure and control, there is a labview based program available from intersil for demonstration of the ISL6112 functionality. user lab test hardware and instrument support is not available. caution: the ISL6112eval1z gets very hot to the touch after operating for a few minutes. the hottest areas are marked on the evaluation board. figure 36. ISL6112eval1z board photo caution hot caution hot caution hot sda scl gnd smi address
ISL6112 fn6456 rev 1.00 page 27 of 30 august 25, 2011 table 11. ISL6112eval1z board components listing component designator component function component description u1 ISL6112 pci-express dual slot hot plug controller q1, q4 voltage rail switches si4405dy or equivalent, p-channel mosfet q2, q3 voltage rail switches si4820dy or equivalent, n-channel mosfet r1, r3, r6, r8 current sense resistor 0.020 ? 1%, 2512 r9, r10, r17, r20 pull-up resistors on forceon and gpi inputs 100k ? , 0201 r11, r12, r13, 14, r15, r16, r18, 19, r21 i/o pull-up resistors 10k ? , 0201 r2, r4, r5, r7 fet gate series resistance 15 ? , 0201 c1, c7, c8, c13 fet gate capacitance 22nf 10%, 16v, 0402 c3, c5, c6, c10, c11, c14 main and vstby decoupling capacitance 1f 10%, 6.3v, 0402 c2, c12 p-fet gate to drain capacitance 6.8nf 10%, 6.3v, 0201 c4, c9 cfilter capacitance (5ms) 0.01f 10%, 6.3v, 0201 r24, r25 aux load resistance 10w 20%, 3w c17, c18 aux load capacitance 100f 20%, 25v, radial electrolytic r22, r26, r28, 29 12main load resistance 20w 20%, 10w r23, r27 3main load resistance 2w 20%, 10w c15, c16, c19, c20 12main and 3main load ca pacitance 470f 20%, 16v, radial electrolytic
fn6456 rev 1.00 page 28 of 30 august 25, 2011 ISL6112
fn6456 rev 1.00 page 29 of 30 august 25, 2011 ISL6112 intersil products are manufactured, assembled and tested utilizing iso9001 quality systems as noted in the quality certifications found at www.intersil.com/en/suppor t/qualandreliability.html intersil products are sold by description on ly. intersil may modify the circuit design an d/or specifications of products at any time without notice, provided that such modification does not, in intersil's sole judgment, affect the form, fit or function of the product. accordingly, the reader is cautioned to verify that datasheets are current before placing orders. information fu rnished by intersil is believed to be accu rate and reliable. however, no responsib ility is assumed by intersil or its subsidiaries for its use; nor for any infrin gements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com for additional products, see www.intersil.com/en/products.html ? copyright intersil americas llc 2007-2011. all rights reserved. all trademarks and registered trademarks are the property of their respective owners. products intersil corporation is a leader in the design and manufacture of high-performance analog semico nductors. the company's product s address some of the industry's fastest growing markets, such as , flat panel displays, cell phones, handheld products, and noteb ooks. intersil's product families address power management and analog sign al processing functions. go to www.intersil.com/products for a complete list of intersil product families. *for a complete listing of applications, related documentation an d related parts, please see the respective device information page on intersil.com: isl21400 to report errors or suggestions for this datasheet, please go to: www.intersil.com/askourstaff fits are available from our website at: http://rel.intersil.co m/reports/search.php revision history the revision history provided is for inform ational purposes only and is believed to be accurate, but not warranted. please go t o web to make sure you have the latest revision. date revision change 7/12/2011 fn6456.1 ? changed title from ?dual slot pci-express powe r controller" to "dual slot pci-express hot plug controller". ? removed retired parts ISL6112inza and ISL6112inza-t* from ordering information. removed package outline drawing, pin configuration diagram, and ther mal information for tqfp package used for retired parts. 9/30/2007 fn6456.0 initial release
ISL6112 fn6456 rev 1.00 page 30 of 30 august 25, 2011 package outline drawing l48.7x7 48 lead quad flat no-lead plastic package rev 5, 4/10 located within the zone indicate d. the pin #1 indentifier may b e unless otherwise specified, t olerance : decimal 0.05 tiebar shown (if present) i s a non-functional feature. the configuration of the pin #1 identifier is optional, but mus t be between 0.15mm and 0.30mm from the terminal tip. dimension applies to the metalliz ed terminal and is measured dimensions in ( ) for reference only. dimensioning and tolerancing c onform to amse y14.5m-1994. 6. either a mold or mark feature. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: 7.00 b a 7.00 (4x) 0.15 index area pin 1 top view pin #1 index area 44x 0.50 4x 5.5 48 37 4. 30 0 . 15 1 36 25 48x 0 . 40 0 . 1 4 m 0.10 c ab 13 24 bottom view 12 5 0 . 2 ref 0 . 00 min. 0 . 05 max. detail "x" c 0 . 90 0 . 1 base plane see detail "x" c c 0.08 seating plane c 0.10 side view typical recommended land pattern 6 6 ( 6 . 80 typ ) ( 4 . 30 ) ( 48x 0 . 60 ) ( 44x 0 . 5 ) ( 48x 0 . 23 ) 0.23 +0.07 / -0.05

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